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FEATURES Low Offset Voltage: 200 V max High Current Gain: 400 min Excellent Current Gain Match: 2% max Low Noise Voltage at 100 Hz, 1 mA: 2.5 nV/Hz max Excellent Log Conformance: rBE = 0.6 max Matching Guaranteed for All Transistors Available in Die Form
Matched Monolithic Quad Transistor MAT04
PIN CONNECTIONS 14-Lead Cerdip (Y Suffix) 14-Lead Plastic DIP (P Suffix) 14-Lead SO (S Suffix)
PRODUCT DESCRIPTION
The MAT04 is a quad monolithic NPN transistor that offers excellent parametric matching for precision amplifier and nonlinear circuit applications. Performance characteristics of the MAT04 include high gain (400 minimum) over a wide range of collector current, low noise (2.5 nV/Hz maximum at 100 Hz, IC = 1 mA) and excellent logarithmic conformance. The MAT04 also features a low offset voltage of 200 V and tight current gain matching, to within 2%. Each transistor of the MAT04 is individually tested to data sheet specifications. For matching parameters (offset voltage, input offset current, and gain match), each of the dual transistor combinations are
verified to meet stated limits. Device performance is guaranteed at 25C and over the industrial and military temperature ranges. The long-term stability of matching parameters is guaranteed by the protection diodes across the base-emitter junction of each transistor. These diodes prevent degradation of beta and matching characteristics due to reverse bias base-emitter current. The superior logarithmic conformance and accurate matching characteristics of the MAT04 makes it an excellent choice for use in log and antilog circuits. The MAT04 is an ideal choice in applications where low noise and high gain are required.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
MAT04-SPECIFICATIONS
(@ TA = 25 C unless otherwise noted. Each transistor is individually tested. For matching parameters (VOS, IOS, hFE) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless otherwise noted.)
Parameter Current Gain Current Gain Match Offset Voltage Offset Voltage Change vs. Collector Current Offset Voltage Change vs. VCB Bulk Emitter Resistance Input Bias Current Input Offset Current Breakdown Voltage Collector Saturation Voltage Collector-Base Leakage Current Noise Voltage Density Symbol hFE hFE VOS VOS/IC VOS/VCB rBE IB IOS BVCEO VCE(SAT) ICBO en fT COBO CEBO Conditions 10 A IC 1 mA 0 V VCB 30 V1 IC = 100 A 0 V VCB 30 V2 10 A IC 1 mA 0 V VCB 30 V3 10 A IC 1 mA VCB = 0 V3 10 A IC 1 mA 0 V VCB 30 V3 10 A IC 1 mA VCB = 0 V4 IC = 100 A 0 V VCB 30 V IC = 100 A; VCB = 0 V IC = 10 A IB = 100 A; IC = 1 mA VCB = 40 V VCB = 0 V; fO = 10 Hz IC = 1 mA; fO = 100 Hz fO = 1 kHz5 IC = 1 mA; VCE = 10 V VCB = 15 V; IE = 0 f = 1 MHz VBE = 0 V; IC = 0 f = 1 MHz MAT04E Min Typ Max 400 800 0.5 50 5 50 0.4 125 0.6 40 0.03 5 2 1.8 1.8 300 10 40 0.06 3 2.5 2.5 2 200 25 100 0.6 250 5 40 0.03 5 2 1.8 1.8 300 10 40 0.06 4 3 3 Min 300 MAT04F Typ Max 600 1 100 10 100 0.4 165 2 4 400 50 200 0.6 330 13 % V V V nA nA V V pA nV/Hz nV/Hz nV/Hz MHz pF pF Unit
ELECTRICAL CHARACTERISTICS
Gain Bandwidth Product Output Capacitance Input Capacitance
NOTES 1 Current gain measured at I C = 10 A, 100 A and 1 mA.
2
Current gain match is defined as:
hFE =
100( IB )(hFE IC
MIN
)
Measured at I C = 10 A and guaranteed by design over the specified range of I C. Guaranteed by design. 5 Sample tested.
3 4
Specifications subject to change without notice.
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MAT04 ELECTRICAL CHARACTERISTICS (at -25 C T
Parameter Symbol Conditions
85 C for MAT04E, -40 C TA 85 C for MAT04F, unless A otherwise noted. Each transistor is individually tested. For matching parameters (VOS, IOS) each dual transistor combination is verified to meet stated limits. All tests made at endpoints unless otherwise noted.)
MAT04E Min Typ Max MAT04F Min Typ Max Unit
Current Gain Offset Voltage Average Offset Voltage Drift Input Bias Current Input Offset Current Average Offset Current Drift Breakdown Voltage Collector-Base Leakage Current Collector-Emitter Leakage Current Collector-Substrate Leakage Current
hFE VOS TCVOS IB IOS TCIOS BVCEO ICBO ICES ICS
10 A IC 1 mA 0 V VCB 30 V1 10 A IC 1 mA 0 V VCB 30 V2 IC = 100 A VCB = 0 V3 IC = 100 A 0 V VCB 30 V IC = 100 A VCB = 0 V IC = 100 A VCB = 0 V IC = 10 A VCB = 40 V VCE = 40 V
225 625 60 0.2 260 1
200 500 120 520 0.4 2 V V/C nA nA pA/C V nA nA nA
160 445 4 50 40 0.5 5 40 20
200 500 8 100 40
0.5 5 0.7
VCS = 40 V 0.7
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MAT04
ABSOLUTE MAXIMUM RATINGS 1
Collector-Base Voltage (BVCBO) . . . . . . . . . . . . . . . . . . . 40 V Collector-Emitter Voltage (BVCEO) . . . . . . . . . . . . . . . . . 40 V Collector-Collector Voltage (BVCC) . . . . . . . . . . . . . . . . . 40 V Emitter-Emitter Voltage (BVEE) . . . . . . . . . . . . . . . . . . . 40 V Collector Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Emitter Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 mA Substrate (Pin-4 to Pin-11) Current . . . . . . . . . . . . . . . 30 mA Operating Temperature Range MAT04EY . . . . . . . . . . . . . . . . . . . . . . . . . -25C to +85C MAT04FY, FP, FS . . . . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Y Package . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +150C P Package . . . . . . . . . . . . . . . . . . . . . . . . . -65C to +125C Lead Temperature (Soldering, 60 sec) . . . . . . . . . . . . +300C
2
DICE CHARACTERISTICS
1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Q1 COLLECTOR Q1 BASE Q1 EMITTER SUBSTRATE Q2 EMITTER Q2 BASE Q2 COLLECTOR Q3 COLLECTOR Q3 BASE Q3 EMITTER SUBSTRATE Q4 EMITTER Q4 BASE Q4 COLLECTOR
Package Type 14-Lead Cerdip 14-Lead Plastic DIP 14-Lead SO
JA
JC
Units C/W C/W C/W
Die Size 0.060 x 0.060 Inch, 3600 Sq. mm (1.52 x 1.52 mm, 2.31 sq. mm)
108 83 120
16 39 36
NOTES 1 Absolute maximum ratings apply to both DICE and packaged parts, unless otherwise noted. 2 JA is specified for worst case mounting conditions, i.e., JA is specified for device in socket for cerdip and P-DIP packages; JA is specified for device soldered to printed circuit board for SO package.
ORDERING GUIDE
Model MAT04EY* MAT04FY* MAT04FP MAT04FS
TA = 25 C VOS max 200 V 400 V 400 V 400 V
Temperature Range -25C to +85C -40C to +85C -40C to +85C -40C to +85C
Package Description Cerdip Cerdip P-DIP-14 14-Lead SO
Package Option Q-14 Q-14 N-14 SO-14
NOTES *Not for new designs; obsolete April 2002.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the MAT04 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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Typical Performance Characteristics- MAT04
TPC 1. Current Gain vs. Collector Current
TPC 2. Current Gain vs. Temperature
TPC 3. Gain Bandwidth vs. Collector Current
TPC 4. Base-Emitter-On-Voltage vs. Collector Current
TPC 5. Small Signal Input Resistance (hie) vs. Collector Current
TPC 6. Small Signal Output Conductance vs. Collector Current
TPC 7. Saturation Voltage vs. Collector Current
TPC 8. Noise Voltage Density vs. Frequency
TPC 9. Noise Voltage Density vs. Collector Current
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MAT04
TPC 10. Total Noise vs. Collector Current
TPC 11. Collector-to-Base Capacitance vs. Collector-toBase Voltage
TPC 12. Collector-to-Substrate Capacitance vs. Collector-toSubstrate Voltage
APPLICATION NOTES
It is recommended that one of the substrate pins (Pins 4 and 11) be tied to the most negative circuit potential to minimize coupling between devices. Pins 4 and 11 are internally connected.
APPLICATIONS CURRENT SOURCES
The MAT04 can be used to implement a variety of high impedance current mirrors as shown in Figures 1, 2, and 3. These current mirrors can be used as biasing elements and load devices for amplifier stages.
Figure 2. Current Mirror, IOUT = 2(lREF)
Figure 1. Unity Gain Current Mirror, IOUT = IREF
Figure 3. Current Mirror, IOUT = 1/2(IREF)
The unity-gain current mirror of Figure 1 has an accuracy of better than 1% and an output impedance of over 100 M at 100 A. Figures 2 and 3 show modified current mirrors designed for a current gain of two, and one-half respectively. The accuracy of these mirrors is reduced from that of the unity-gain source due to base current errors but is still better than 2%.
Figure 4 is a temperature independent current sink that has an accuracy of better than 1% at an output current of 100 A to 1 mA. The Schottky diode acts as a clamp to ensure correct circuit start-up at power on. The resistors used in this circuit should be 1% metal-film type.
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MAT04
Figure 4. Temperature Independent Current Sink, IOUT = 10 V/R
NONLINEAR FUNCTIONS
An application where precision matched-transistors are a powerful tool is in the generation of nonlinear functions. These circuits are based on the transistor's logarithmic property, which takes the following idealized form:
VOUT =
1 2
VA + VB
2
2
VBE =
kT lC In q lS
This circuit uses two MAT04 and maintains an accuracy of better than 0.5% over an input range of 10 mV to 10 V. The layout of the MAT04s reduces errors due to matching and temperature differences between the two precision quad matched transistors. Op amps A1 and A2 translate the input voltages into logarithmic valued currents (IA and IB in Figure 5) that flow through transistor Q3 and Q5. These currents are summed by transistor Q4 (IO = IA + IB = l12 + l22 ), which feeds the current-to-voltage converter consisting of op amp A3. To maintain accuracy, 1% metal-film resistors should be used.
The MAT04, with its excellent logarithmic conformance, maintains this idealized function over many decades of collector current. This, in addition to the stringent parametric matching of the MAT04, enables the implementation of extremely accurate log/antilog circuits. The circuit of Figure 5 is a vector summer that adds and subtracts logged inputs to generate the following transfer function:
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MAT04
Figure 5. Vector Summer
LOW NOISE, HIGH SPEED INSTRUMENTATION AMPLIFIER Table I. Instrumentation Amplifier Characteristics
The circuit of Figure 6 is a very low noise, high speed amplifier, ideal for use in precision transducer and professional audio applications. The performance of the amplifier is summarized in Table I. Figure 7 shows the input referred spot noise over the 0-25 kHz bandwidth to be flat at 1.2 nV/Hz. Figure 20 highlights the low 1/f noise corner at 2 Hz. The circuit uses a high speed op amp, the OP17, preceded by an input amplifier. This consists of a precision dual matchedtransistor, the MAT02, and a feedback V-to-I converter, the MAT04. The arrangement of the MAT04 is known as a "linearized cross quad" which performs the voltage-to-current conversion. The OP17 acts as an overall nulling amplifier to complete the feedback loop. Resistors R1, R2, and R3, R4 form voltage dividers that attenuate the output voltage swing since the "cross quad" arrangement has a limited input range. Biasing for the input stage is set by Zener diode Z1. At low currents, the effective zener voltage is about 3.3 V due to the soft knee characteristic of the Zener diode. This results in a bias current of 530 A per side for the input stage. The gain of this amplifier with the values shown in Figure 6 is:
VOUT 33000 = VIN RG
Input Noise Voltage Density Bandwidth
G = 1000 G = 100 G = 10 G = 500 G = 100 G = 10
1.2 nV/Hz 3.6 nV/Hz 30 nV/Hz 400 kHz 1 MHz 1.2 MHz 40 V/s 130 dB 0.03% 10 s 350 mW
Slew Rate Common-Mode Rejection G = 1000 Distortion Settling Time Power Consumption G = 100 f = 20 Hz to 20 kHz G = 1000
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MAT04
Figure 6. Low Noise, High-Speed Instrumentation Amplifier
Figure 7. Spot Noise of the Instrumentation Amplifier from 0-25 kHz, Gain Of 1000
Figure 8. Low Frequency Noise Spectrum Showing Low 2 Hz Noise Corner, Gain = 1000
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MAT04
Figure 9. Voltage-Controlled Attenuator
VOLTAGE-CONTROLLED ATTENUATOR
The voltage-controlled attenuator (VCA) of Figure 9, widely used in professional audio circles, can easily be implemented using a MAT04. The excellent matching characteristics of the MAT04 enables the VCA to have a distortion level of under 0.03% over a wide range of control voltages. The VCA accepts a 3 V RMS input and easily handles the full 20 Hz-20 kHz audio bandwidth as shown in Figure 10. Noise level for the VCA is more than 110 dB below maximum output. In the voltage controlled attenuator, the input signal modulates the stage current of each differential pair. Op amps A2 and A3 in conjunction with transistors Q5 and Q6 form voltage-to-current converters that transform a single input voltage into differential currents which form the stage currents of each differential pair. The control voltage shifts the current between each side of the two differential pairs, regulating the signal level reaching the output stage which consists of op amp A1. Figure 11 shows the increase in signal attenuation as the control voltage becomes more negative.
The ideal transfer function for the voltage-controlled attenuator is:
VOUT / IN =
2 R14 1 + exp(VCONTROL ) R13 + R14 kT q
Where k = Boltzman constant 1.38 x 10-23J/K T = temperature in K q = electronic charge = 1.602 x 10-19C From the transfer function it can be seen that the maximum gain of the circuit is 2 (6 dB). To ensure best performance, resistors R2 through R7 should be 1% metal film resistors. Since capacitor C2 can see small amounts of reverse bias when the control voltage is positive, it may be prudent to use a nonpolarized tantalum capacitor.
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MAT04
Figure 10. Voltage-Controlled Attenuator, Attenuation vs. Frequency
Figure 11. Voltage-Controlled Attenuator, Attenuation vs. Control Voltage
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
14-Lead Cerdip (Q-14)
0.005 (0.13) MIN
14
0.098 (2.49) MAX
8
0.310 (7.87) 0.220 (5.59)
1 7
PIN 1 0.785 (19.94) MAX 0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN
0.320 (8.13) 0.290 (7.37)
0.100 0.070 (1.78) SEATING (2.54) 0.030 (0.76) PLANE BSC
15 0
0.015 (0.38) 0.008 (0.20)
14-Lead Plastic DIP (N-14)
0.795 (20.19) 0.725 (18.42)
14 1 8 7
14-Lead Narrow-Body SO (R-14/SO-14)
0.3444 (8.75) 0.3367 (8.55)
0.280 (7.11) 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.130 (3.30) MIN
PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356)
0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93)
0.1574 (4.00) 0.1497 (3.80)
14 1
8 7
0.2440 (6.20) 0.2284 (5.80)
PIN 1 0.0098 (0.25) 0.0040 (0.10)
0.015 (0.381) 0.008 (0.204)
0.0688 (1.75) 0.0532 (1.35)
0.0196 (0.50) x 45 0.0099 (0.25)
0.100 0.070 (1.77) (2.54) 0.045 (1.15) BSC
SEATING PLANE
SEATING PLANE
0.0500 (1.27) BSC
0.0192 (0.49) 0.0138 (0.35)
0.0099 (0.25) 0.0075 (0.19)
8 0
0.0500 (1.27) 0.0160 (0.41)
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MAT04 Revision History
Location Data Sheet changed from REV. C to REV. D. Page
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Deleted WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Edits to TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5-6 Added OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
C00285-0-2/02(D) PRINTED IN U.S.A.
Deleted ELECTRICAL CHARACTERISTICS for -55C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
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